SEMICONDUCTOR MEMORY APPARATUS

A semiconductor memory apparatus of the present invention comprises: a resistive memory cell connected between a bit line and a bit line bar; a control part for connecting the bit line to a first node, in response to a first sense amplifier enable signal and a second sense amplifier enable signal, and applying reference voltage to a second node; a data output sense amplifier for sensing and amplifying the voltage of the first node and that of the second node; a data transmitting part for connecting the first and second nodes to a data line and a data line bar, respectively, in response to a column selection signal; and a data input unit for driving the bit line and the bit line bar according to voltage levels of the first and second nodes, in response to a light enable signal. [Reference numerals] (100) Resistive memory device; (700) Data input unit