SELECTIVE CAPPING OF METAL INTERCONNECT LINES DURING AIR GAP FORMATION

Provided are methods and systems for forming air gaps in an interconnect layer between adjacent conductive lines. Protective layers may be selectively formed on exposed surfaces of the conductive lines, while structures in between the lines may remain unprotected. These structures may be made from a...

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Bibliographische Detailangaben
Hauptverfasser: SPURLIN TIGHE A, SRIRAM MANDYAM, ANTONELLI GEORGE A, SUBRAMONIUM PRAMOD, CHATTOPADHYAY KAUSHIK
Format: Patent
Sprache:eng ; kor
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Zusammenfassung:Provided are methods and systems for forming air gaps in an interconnect layer between adjacent conductive lines. Protective layers may be selectively formed on exposed surfaces of the conductive lines, while structures in between the lines may remain unprotected. These structures may be made from a sacrificial material that is later removed to form voids. In certain embodiments, the structures are covered with a permeable non-protective layer that allows etchants and etching products to pass through during removal. When a work piece having a selectively formed protective layer is exposed to gas or liquid etchants, these etchants remove the sacrificial material without etching or otherwise impacting the metal lines. Voids formed in between these lines may be partially filled with a dielectric material to seal the voids and/or protect sides of the metal lines. Additional interconnect layers may be formed on a processed layer containing the air gaps. [Reference numerals] (411) I/O ESD RC-clamp;(413) Core ESD RC-clamp;(427) Blocking circuit;(AA,BB) ESD design path from VDD1 to VDD2;(CC) VDD2(Core);(DD) VSS2(Core)