METHOD OF ANALYZING COUPLING EFFECT OF INTEGRATED CIRCUIT

PURPOSE: A method for analyzing a coupling effect of an integrated circuit is provided to precisely calculate the coupling effect of sacrifice wires in the integrated circuit. CONSTITUTION: An integrated circuit selects second wires having effective coupling capacitance between a first wire and wire...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: YUN, YEO IL, PARK, SANG HO, MIN, SEONG UK
Format: Patent
Sprache:eng ; kor
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PURPOSE: A method for analyzing a coupling effect of an integrated circuit is provided to precisely calculate the coupling effect of sacrifice wires in the integrated circuit. CONSTITUTION: An integrated circuit selects second wires having effective coupling capacitance between a first wire and wires around the first wire (S100). The integrated circuit selects test signal patterns of the first wire and the second wires from signal patterns (S200). The integrated circuit calculates a coupling noise of the first wire or a coupling transition delay based on the test signal patterns (S300). [Reference numerals] (AA) Start; (BB) End; (S100) Select second wires having effective coupling capacitance between a first wire and wires around the first wire; (S200) Select test signal patterns of the first wire and the second wires from signal patterns; (S300) Calculate a coupling noise of the first wire or a coupling transition delay based on the test signal patterns