SCRAMBLER IN NEXT GENERATION DSRC SYSTEM AND VELOCITY ELEVATION METHOD OF THE SAME
PURPOSE: A scrambler of a next-generation DSRC(Dedicated Short Range Communication) system and a speed improvement method thereof are provided to encode transmission frame data which is transmitted from a user who does not have a cryptography key, thereby preventing generation of a bit block having...
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Format: | Patent |
Sprache: | eng ; kor |
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Zusammenfassung: | PURPOSE: A scrambler of a next-generation DSRC(Dedicated Short Range Communication) system and a speed improvement method thereof are provided to encode transmission frame data which is transmitted from a user who does not have a cryptography key, thereby preventing generation of a bit block having a repetitive pattern. CONSTITUTION: A shift register(110) of a scramble table generation device(100) generates 16 scramble key values and generates 127 scramble key values by shift of the generated scramble key values. A first XOR gate unit(120) generates a bit value as much as 1byte by first XOR computation of a scramble key value or a scramble start key value per shift operation. The first XOR gate unit defines the 127 scramble key values in a scramble table in advance by assigning the same in a memory. A second XOR gate unit(210) of a scrambling unit(200) outputs output data in parallel by second XOR computation of input data and an extracted scramble key value. [Reference numerals] (110) Shift register; (120) First XOR gate unit; (210) Second XOR gate unit; (AA) Input data(Ib0-Ib7); (BB) Output data(Ob0-Ob7) |
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