METHOD FOR DECODING AN ADDRESS AND SEMICONDUCTOR DEVICE USING THE SAME

PURPOSE: An address decoding method and a semiconductor memory device are provided to prevent a read operation fail and a write operation fail by generating an output enable signal synchronized with a rising edge of a strobe block. CONSTITUTION: A strobe clock generating unit(10) generates a strobe clock whose delay amount is controlled according to first to third test mode signals which are selectively enabled in response to a read signal or a write signal. An internal address generating unit(20) latches an address in response to a first level of the strobe clock and decodes the address in response to a second level of the strobe clock. An output enable signal generating unit(30) generates an output enable signal which is selectively enabled by decoding an internal address. [Reference numerals] (10) Strobe clock generating unit; (21) First internal address generating unit; (22) Second internal address generating unit; (30) Output enable signal generating unit