CHIP PACKAGE MEMBER AND MANUFACTURING METHOD THEREOF

CHIP PACKAGE MEMBER AND MANUFACTURING METHOD THEREOF

PURPOSE: A chip package member and a manufacturing method thereof are provided to generate a chip package which is robust against external stress by forming a plating layer with metal including cobalt. CONSTITUTION: A chip package member includes a circuit pattern layer(220) and an insulation layer(...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: KANG, TEA HYUK
Format: Patent
Sprache:eng ; kor
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:PURPOSE: A chip package member and a manufacturing method thereof are provided to generate a chip package which is robust against external stress by forming a plating layer with metal including cobalt. CONSTITUTION: A chip package member includes a circuit pattern layer(220) and an insulation layer(210). The insulation layer is bonded to a bonding region of the circuit pattern layer. A first mask layer is formed on the insulation layer of the chip package member. The chip package member is plated with the first metal(S50). The first mask layer is separated from the insulation layer. A second mask layer is formed on the circuit pattern layer. The chip package member is plated with the second metal(S60).