LOW AREA WRAPPER CELL FOR PARALLEL TESTING OF HIERARCHICAL SOC

PURPOSE: A low area wrapper cell for a parallel test of a hierarchical SoC is provided to improve SoC yield by using a small number of multiplexers and flip flops for the parallel test of the hierarchical SoC. CONSTITUTION: A wrapper cell includes a first input for receiving a first data signal, a first output for outputting the first data signal, a second input and a third input for receiving a test pattern, and a second output and a third output for outputting the test pattern. A first multiplexer(412) includes an input connected to a first flip flop and the first input and an output connected to the first output. A second multiplexer(414) has an input connected to the first input and the third input and the output connected to the second flip flop. The first flip flop has the input connected to the second input and the output connected to the lower input of the first multiplexer. A second flip flop(418) has the input connected to the output of a second multiplexer and the output connected to the third output.