METHOD FOR EXPOSING THROUGH-BASE WAFER VIAS FOR FABRICATION OF STACKED DEVICES

PURPOSE: A method for exposing a through base wafer via for manufacturing the stack apparatus is provided to reduce the silicon tailing after CMP process. CONSTITUTION: A base wafer having a front side and a back side is arranged. The base wafer comprises one or more conductive vias. The front side...

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Bibliographische Detailangaben
Hauptverfasser:	LEE, JUNG HEE, HENRY JAMES MATTHEW, CASTILLO DANIEL HERNANDEZ II, KIM, HYOUNG SIK
Format:	Patent
Sprache:	eng ; kor
Schlagworte:	ADHESIVES BASIC ELECTRIC ELEMENTS CHEMISTRY DRESSING OR CONDITIONING OF ABRADING SURFACES DYES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS GRINDING MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FORELSEWHERE METALLURGY MISCELLANEOUS APPLICATIONS OF MATERIALS MISCELLANEOUS COMPOSITIONS NATURAL RESINS PAINTS PERFORMING OPERATIONS POLISHES POLISHING SEMICONDUCTOR DEVICES TRANSPORTING
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Beschreibung
Zusammenfassung:	PURPOSE: A method for exposing a through base wafer via for manufacturing the stack apparatus is provided to reduce the silicon tailing after CMP process. CONSTITUTION: A base wafer having a front side and a back side is arranged. The base wafer comprises one or more conductive vias. The front side of the base wafer is attached to the carrier. The back side of the base wafer touches the grinding pad and the CMP slurry. The back side of the base wafer is polished.