MANUFACTURING METHOD OF GATE PATTERN FOR SEMICONDUCTOR DEVICE
PURPOSE: A method for forming the gate pattern of a semiconductor device is provided to reduce the resistance of the gate pattern by forming a control gate with a first metal nitride layer and a metal layer. CONSTITUTION: A tunnel insulation layer(103), and a floating gate layer(105) and a dielectri...
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Format: | Patent |
Sprache: | eng ; kor |
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Zusammenfassung: | PURPOSE: A method for forming the gate pattern of a semiconductor device is provided to reduce the resistance of the gate pattern by forming a control gate with a first metal nitride layer and a metal layer. CONSTITUTION: A tunnel insulation layer(103), and a floating gate layer(105) and a dielectric layer(107) are formed on a semiconductor substrate. A first metal nitride layer(109) is formed on the dielectric film. A hard mask pattern is formed on the first metal nitride layer. The floating gate layer, the dielectric layer and the first metal nitride layer are etched to form a laminate pattern using the hard mask pattern as an etching mask. A groove which exposes the first metal nitride layer is formed by removing the hard mask pattern. The groove is filled with a metal layer(119) to form a control gate which includes a second metal nitride layer(117), and the first metal nitride layer and the metal layer. |
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