FAST FOURIER TRANSFORM/INVERSE FAST FOURIER TRANSFORM OPERATING CORE

PURPOSE: A fast Fourier transform/inverse fast Fourier transform operating core is provided to minimize a necessary memory capacity by sharing one FFT/IFFT calculation core. CONSTITUTION: In a device, a first MUX(MUX1) multiplexes one of input sequence of a first FFT and a third FFT. An input buffer...

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Bibliographische Detailangaben
1. Verfasser:	HWANG, CHANG IK
Format:	Patent
Sprache:	eng
Schlagworte:	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY MULTIPLEX COMMUNICATION
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	PURPOSE: A fast Fourier transform/inverse fast Fourier transform operating core is provided to minimize a necessary memory capacity by sharing one FFT/IFFT calculation core. CONSTITUTION: In a device, a first MUX(MUX1) multiplexes one of input sequence of a first FFT and a third FFT. An input buffer(110) stores the input sequence of the first FFT and outputs it, and a computation block(120) includes a plurality of calculation stages. The plural calculation stages response indication(DIT/DIF) and by-pass indication(BP) of a signal processing method, and it changes the input sequence of the first FFT and the third FFT and generates an output sequence respectively. The plural calculation stages changes an input sequence of the second IFFT and generates the output sequence of the second IFFT. A control block(130) generates a indication signal for processing a signal and a by-pass signal.