PROCESSOR WITH RECONFIGURABLE FLOATING POINT UNIT

PROCESSOR WITH RECONFIGURABLE FLOATING POINT UNIT

A technique of operating a processor (100) includes determining whether a floating point unit (FPU) (120) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into a single operation, when the full-bit mode is indicated, or...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: AHMED ASHRAF, CLARK MICHAEL, ILIC JELENA, GOVEAS KELVIN DOMNIC
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A technique of operating a processor (100) includes determining whether a floating point unit (FPU) (120) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into a single operation, when the full-bit mode is indicated, or multiple operations, when the reduced-bit mode is indicated.