FABRICATION METHOD OF SEMICONDUCTOR DEVICE
PURPOSE: A fabrication method of a semiconductor device is provided to simplify a process and reduce time and costs by applying one of two silicide barriers to one dual stress liner. CONSTITUTION: In a fabrication method of a semiconductor device, a gate electrode(110) and source/drain regions(104,1...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PURPOSE: A fabrication method of a semiconductor device is provided to simplify a process and reduce time and costs by applying one of two silicide barriers to one dual stress liner. CONSTITUTION: In a fabrication method of a semiconductor device, a gate electrode(110) and source/drain regions(104,106) are formed on a first MOS area and a second MOS area opposite to the first MOS area. A silicide barrier is formed on the second MOS area while exposing the first MOS area. A first metal silicide(108) is formed on the gate electrode and a source/drain region of the first MOS area. A first stress(124) is formed on the first MOS area, and a second metal silicide is formed on a gate electrode and a source/drain region of an exposed second MOS area. A second stress liner(126) is formed on the second MOS area in which the second metal silicide is formed. |
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