METHOD FOR LAYOUT DE-COUPLING CAPACITOR OF A SEMICONDUCTOR MEMORY DEVICE

A layout method of a decoupling capacitor of a semiconductor memory device is provided to improve performance of a decoupling capacitor by facilitating a power connection through gate layout of the decoupling capacitor. A layout region(300) of a decoupling capacitor for forming the decoupling capacitor is laid out into a square pattern. A first power is applied to a plurality of decoupling capacitors. A second power(M0,M1) is supplied to blocks(B1,B2) adjacent to the layout region of the decoupling capacitor. A width of each decoupling capacitor corresponding to the second power is changeably laid out. A subs layer is overlapped in a gate and an active of the decoupling capacitor. A metal line and a contact(C) are laid out for supplying a power to the gate and the active of the decoupling capacitor. The first power is applied to the gate of the decoupling capacitor.