METHOD OF FORMING A DUAL DAMASCENE PATTERN IN SEMICONDUCTOR DEVICE
A method for forming a dual damascene pattern of a semiconductor device is provided to minimize a sputtering etching property by minimizing energetic ion energy in forming a dual damascene pattern. An interlayer insulation film(102) is formed on a semiconductor substrate(100). A contact hole(106) is...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A method for forming a dual damascene pattern of a semiconductor device is provided to minimize a sputtering etching property by minimizing energetic ion energy in forming a dual damascene pattern. An interlayer insulation film(102) is formed on a semiconductor substrate(100). A contact hole(106) is formed by etching the interlayer insulation film. A protective film is formed on the interlayer insulation film including the contact hole in order to fill the contact hole. The protective film formed on the interlayer insulation film of a region on which a trench(112) is formed is etched. The trench having a width wider than the contact hole is formed by isotropically etching an exposed interlayer insulation film. |
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