MEMORY ARRAY ON MORE THAN ONE DIE
A memory array on more than one die and method of the same is provided to reduce the latency size and/or the power consumption by designing the common line of the short length. The memory circuit comprises a memory array(102) and an access control circuit(104), and the memory array comprises a plura...
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| creator | RUPLEY JEFFERY P. II TAUFIQUE MOHAMMED H BLACK BRYAN MCCAULEY DONALD W LOH GABRIEL H DEVALE JOHN P JALLICE DERWIN BREKELBAUM EDWARD A |
| description | A memory array on more than one die and method of the same is provided to reduce the latency size and/or the power consumption by designing the common line of the short length. The memory circuit comprises a memory array(102) and an access control circuit(104), and the memory array comprises a plurality of memory cells. The access control circuit controls the access to the memory cell of the memory array. The first die(111) comprises a plurality of first memory cells(121,122,131,132). The second die(112) comprises a plurality of second memory cells(126,127,136,137). The second die comprises the common line(125), which is used in order to supply the digital signal to the memory cell of the first and the second memory cell. |
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II</au><au>TAUFIQUE MOHAMMED H</au><au>BLACK BRYAN</au><au>MCCAULEY DONALD W</au><au>LOH GABRIEL H</au><au>DEVALE JOHN P</au><au>JALLICE DERWIN</au><au>BREKELBAUM EDWARD A</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MEMORY ARRAY ON MORE THAN ONE DIE</title><date>2009-01-12</date><risdate>2009</risdate><abstract>A memory array on more than one die and method of the same is provided to reduce the latency size and/or the power consumption by designing the common line of the short length. The memory circuit comprises a memory array(102) and an access control circuit(104), and the memory array comprises a plurality of memory cells. The access control circuit controls the access to the memory cell of the memory array. The first die(111) comprises a plurality of first memory cells(121,122,131,132). The second die(112) comprises a plurality of second memory cells(126,127,136,137). The second die comprises the common line(125), which is used in order to supply the digital signal to the memory cell of the first and the second memory cell.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
| title | MEMORY ARRAY ON MORE THAN ONE DIE |
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