MULTI-SEMICONDUCTOR CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

MULTI-SEMICONDUCTOR CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

A multi-chip package and a manufacturing method thereof are provided to interpose a metal spacer between a plurality of semiconductor chips and secure a wire loop gap and release the heat of semiconductor chips rapidly to outside in order to make the operation of the semiconductor chip smooth. A mul...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: JO, SANG GUI
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A multi-chip package and a manufacturing method thereof are provided to interpose a metal spacer between a plurality of semiconductor chips and secure a wire loop gap and release the heat of semiconductor chips rapidly to outside in order to make the operation of the semiconductor chip smooth. A multi-chip package(100) comprises a metal plate(120), a plurality of semiconductor chips(130,140), and a spacer(150). The metal plate is formed according to each unit outer of a substrate. The semiconductor chip is laminated on the upper side of each unit. The spacer is interposed among a plurality of semiconductor chips. The spacer has a connection part(151) connected to the metal plate.