LOW-VOLTAGE DOWN CONVERTER

A low-voltage level converter provides level conversion for multiple-supply voltages for very large scale integration (VLSI) systems. Low voltage-level down conversion is achieved at very low voltage operation for on-chip test circuitry for multiple-supply voltage systems. The converter includes an output driver PMOS PET (212) with its well grounded. An output NMOS FET (214) and an extra input pulldown NMOS FET (216) are connected in parallel to the input (218) of the converter. The extra input pulldown NMOS FET (216) provides a negative gate voltage at its drain (246) to the output driver PMOS FET gate (222). The negative gate voltage and grounded well significantly decrease rise time of the output signal noise pulse of the converter and virtually eliminate a negative spike voltage at the initial transition of the output pulse produced by coupling effect between the input pulse (207) and output pulse (209) due to Miller capacitance effect.