METHOD OF FORMING FIELD EFFECT TRANSISTOR

METHOD OF FORMING FIELD EFFECT TRANSISTOR

A method of forming a field effect transistor is provided to increase the size of a source/drain region of the transistor by using spacers with reduced lateral wall dimension, and reduce the influence of a shot channel effect by forming differently the size of the source\drain region. A gate electro...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: KU, JA HUM, PARK, JAE EON, LEAKE GERALD JR, SUN, MIN CHUL, BAIOCCO CHRISTOPHER VINCENT, YANG, JEONG HWAN, YANG, JONG HO, KO, YOUNG GUN
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A method of forming a field effect transistor is provided to increase the size of a source/drain region of the transistor by using spacers with reduced lateral wall dimension, and reduce the influence of a shot channel effect by forming differently the size of the source\drain region. A gate electrode(16) having electric insulation spacers(20) is formed on a lateral wall. Impurities which are selected from a group consisting of germanium and florin to improve etching are implanted into electric insulation spacers. The electric insulation spacers are subjected to etch back to reduce lateral wall dimensions of the electric insulation spacers. By using the electric insulation spacers with the reduced lateral wall dimensions as an ion implantation mask, source/drain dopants of first conductive type are implanted into a semiconductor substrate(10).