MULTIPROCESSOR SYSTEM

A multiprocessor system is provided to reduce memory read latency in a local node by reducing data/address latency occurring in memory read which is executed in each system board forming an SMP(Symmetric Multiple Processors) structure assigning tasks to all CPUs symmetrically. A determiner determines whether a read command issued from a CPU(1) and inputted to a global address crossbar(8) is the read command for a memory(2) installed in the system board. An executor executes the read command before global access based on the address notified from the global address crossbar when the inputted read command is the read command for the internal memory. A setting part sets the data read from the memory to be queued to a data queue formed in a CPU side without queuing the read data to the data queue formed in a memory side. An orderer orders the data queue formed in the CPU side to discard or transmit the data to the CPU based on notification received from the global address crossbar.