DIGITAL TO ANALOG CONVERTER THAT MINIMISED AREA SIZE AND SOURCE DRIVER INCLUDING THEREOF
A DAC(Digital to Analog Converter) and a source driver having the same are provided to decrease an output error from the DAC by preventing a parasitic capacitance from affecting the DAC. A control logic(30) receives upper bit data and control bit data. A first resistor(11) divides first and second r...
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| creator | KIM, BEOP HEE JUNG, JI WOON JEON, YONG WEON |
| description | A DAC(Digital to Analog Converter) and a source driver having the same are provided to decrease an output error from the DAC by preventing a parasitic capacitance from affecting the DAC. A control logic(30) receives upper bit data and control bit data. A first resistor(11) divides first and second reference voltages and outputs first divided voltages. A first decoder(21) selects one of the first divided voltages corresponding to the upper bit data. A second resistor(12) divides third and fourth reference voltages and outputs plural second divided voltages. A second decoder(22) selects one of the second divided voltages in response to lower bit data. A selector circuit selects one of the second and third reference voltages according to control bit data. A sample and hold circuit outputs an analog voltage in response to output voltages from the first and second decoders and the selector circuit. The control logic controls the first decoder according to the control bit data, so that the output voltage from the first decoder is increased by a predetermined value. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20080012070A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20080012070A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20080012070A3</originalsourceid><addsrcrecordid>eNqNy7EKwjAQgOEsDqK-w4GzEOug65Fc08M2gUsq4lKKxEm0UN8fM_gATv_y_Ut1tew4YQspAHpsgwMT_IUkkUBqMEHHnjuOZAGFECLfqEgLMfRiCKxw0cDetL1l78pEQqFeq8VjfM558-tKbWtKptnl6T3keRrv-ZU_w1kqrU9a7yt91Hj4T30BkrIxzA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>DIGITAL TO ANALOG CONVERTER THAT MINIMISED AREA SIZE AND SOURCE DRIVER INCLUDING THEREOF</title><source>esp@cenet</source><creator>KIM, BEOP HEE ; JUNG, JI WOON ; JEON, YONG WEON</creator><creatorcontrib>KIM, BEOP HEE ; JUNG, JI WOON ; JEON, YONG WEON</creatorcontrib><description>A DAC(Digital to Analog Converter) and a source driver having the same are provided to decrease an output error from the DAC by preventing a parasitic capacitance from affecting the DAC. A control logic(30) receives upper bit data and control bit data. A first resistor(11) divides first and second reference voltages and outputs first divided voltages. A first decoder(21) selects one of the first divided voltages corresponding to the upper bit data. A second resistor(12) divides third and fourth reference voltages and outputs plural second divided voltages. A second decoder(22) selects one of the second divided voltages in response to lower bit data. A selector circuit selects one of the second and third reference voltages according to control bit data. A sample and hold circuit outputs an analog voltage in response to output voltages from the first and second decoders and the selector circuit. The control logic controls the first decoder according to the control bit data, so that the output voltage from the first decoder is increased by a predetermined value.</description><language>eng</language><subject>ADVERTISING ; ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION ; BASIC ELECTRONIC CIRCUITRY ; CODE CONVERSION IN GENERAL ; CODING ; CRYPTOGRAPHY ; DECODING ; DISPLAY ; EDUCATION ; ELECTRICITY ; PHYSICS ; SEALS</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080211&DB=EPODOC&CC=KR&NR=20080012070A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080211&DB=EPODOC&CC=KR&NR=20080012070A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KIM, BEOP HEE</creatorcontrib><creatorcontrib>JUNG, JI WOON</creatorcontrib><creatorcontrib>JEON, YONG WEON</creatorcontrib><title>DIGITAL TO ANALOG CONVERTER THAT MINIMISED AREA SIZE AND SOURCE DRIVER INCLUDING THEREOF</title><description>A DAC(Digital to Analog Converter) and a source driver having the same are provided to decrease an output error from the DAC by preventing a parasitic capacitance from affecting the DAC. A control logic(30) receives upper bit data and control bit data. A first resistor(11) divides first and second reference voltages and outputs first divided voltages. A first decoder(21) selects one of the first divided voltages corresponding to the upper bit data. A second resistor(12) divides third and fourth reference voltages and outputs plural second divided voltages. A second decoder(22) selects one of the second divided voltages in response to lower bit data. A selector circuit selects one of the second and third reference voltages according to control bit data. A sample and hold circuit outputs an analog voltage in response to output voltages from the first and second decoders and the selector circuit. The control logic controls the first decoder according to the control bit data, so that the output voltage from the first decoder is increased by a predetermined value.</description><subject>ADVERTISING</subject><subject>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CODE CONVERSION IN GENERAL</subject><subject>CODING</subject><subject>CRYPTOGRAPHY</subject><subject>DECODING</subject><subject>DISPLAY</subject><subject>EDUCATION</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>SEALS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNy7EKwjAQgOEsDqK-w4GzEOug65Fc08M2gUsq4lKKxEm0UN8fM_gATv_y_Ut1tew4YQspAHpsgwMT_IUkkUBqMEHHnjuOZAGFECLfqEgLMfRiCKxw0cDetL1l78pEQqFeq8VjfM558-tKbWtKptnl6T3keRrv-ZU_w1kqrU9a7yt91Hj4T30BkrIxzA</recordid><startdate>20080211</startdate><enddate>20080211</enddate><creator>KIM, BEOP HEE</creator><creator>JUNG, JI WOON</creator><creator>JEON, YONG WEON</creator><scope>EVB</scope></search><sort><creationdate>20080211</creationdate><title>DIGITAL TO ANALOG CONVERTER THAT MINIMISED AREA SIZE AND SOURCE DRIVER INCLUDING THEREOF</title><author>KIM, BEOP HEE ; JUNG, JI WOON ; JEON, YONG WEON</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20080012070A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>ADVERTISING</topic><topic>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CODE CONVERSION IN GENERAL</topic><topic>CODING</topic><topic>CRYPTOGRAPHY</topic><topic>DECODING</topic><topic>DISPLAY</topic><topic>EDUCATION</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>SEALS</topic><toplevel>online_resources</toplevel><creatorcontrib>KIM, BEOP HEE</creatorcontrib><creatorcontrib>JUNG, JI WOON</creatorcontrib><creatorcontrib>JEON, YONG WEON</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KIM, BEOP HEE</au><au>JUNG, JI WOON</au><au>JEON, YONG WEON</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DIGITAL TO ANALOG CONVERTER THAT MINIMISED AREA SIZE AND SOURCE DRIVER INCLUDING THEREOF</title><date>2008-02-11</date><risdate>2008</risdate><abstract>A DAC(Digital to Analog Converter) and a source driver having the same are provided to decrease an output error from the DAC by preventing a parasitic capacitance from affecting the DAC. A control logic(30) receives upper bit data and control bit data. A first resistor(11) divides first and second reference voltages and outputs first divided voltages. A first decoder(21) selects one of the first divided voltages corresponding to the upper bit data. A second resistor(12) divides third and fourth reference voltages and outputs plural second divided voltages. A second decoder(22) selects one of the second divided voltages in response to lower bit data. A selector circuit selects one of the second and third reference voltages according to control bit data. A sample and hold circuit outputs an analog voltage in response to output voltages from the first and second decoders and the selector circuit. The control logic controls the first decoder according to the control bit data, so that the output voltage from the first decoder is increased by a predetermined value.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING CRYPTOGRAPHY DECODING DISPLAY EDUCATION ELECTRICITY PHYSICS SEALS |
| title | DIGITAL TO ANALOG CONVERTER THAT MINIMISED AREA SIZE AND SOURCE DRIVER INCLUDING THEREOF |
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