STACK TYPE WAFER LEVEL PACKAGE AND METHOD OF MANUFACTURING THE SAME, AND WAFER LEVEL STACK PACKAGE AND METHOD OF MANUFACTURING THE SAME
A stack-type wafer level package, a manufacturing method thereof, and a wafer level stack package and a manufacturing method thereof are provided to improve the productivity and reliability by protruding a penetrating electrode through a single process. A through-hole is formed in a semiconductor ch...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | A stack-type wafer level package, a manufacturing method thereof, and a wafer level stack package and a manufacturing method thereof are provided to improve the productivity and reliability by protruding a penetrating electrode through a single process. A through-hole is formed in a semiconductor chip(210). A conductive pattern(250) consists of a conductive trace(252) formed on the semiconductor chip and electrically connected to the semiconductor chip, and a conductive pad(254) extending from the conductive trace through the through-hole. A conductive bump(260) is formed on the conductive trace at a position corresponding to an upper portion of the conductive pad. The conductive pad has a lower end which is flush with a bottom surface of the semiconductor chip. |
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