MATRIX MULTIPLY WITH REDUCED BANDWIDTH REQUIREMENTS

Matrix multiplication with reduced bandwidth requirements is provided to reduce a memory bandwidth to execute a multiply-add operation by including a broadcast mechanism of operands in a multi-threaded processing. Matrix multiplication with reduced bandwidth requirements includes the steps of: acquiring a first value specified by the broadcast operands included together in the set of operations; offering the first value to multiple program command execution units(183); acquiring a set of second values specified by a parallel operands included together in the set of operations, wherein each of the second values is corresponded to the one of the multiple threads of lanes; offering the one of the second values in the set of the second values to the every multiple program command execution units; and executing the set of the operations about each of the multiple threads or lanes.