NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR OPERATING SAME

A nonvolatile semiconductor storage device provided with a highly integrated memory cell array wherein consumption current increase caused by a transient current due to potential change of a bit line and a word line is suppressed during shifts among modes of reading, writing and erasing. A two-terminal memory cell is provided with a variable resistance element whose resistance value reversibly changes by pulse application. In the memory cell array (1), a plurality of two-terminal memory cells are arranged in a row direction and a column direction, respectively, and ends on one side of the memory cells on a same row are connected to common word lines (WL1-WLn), and the other ends of the memory cells on a same column are connected to common bit lines (BL1-BLm). While the operation of reading, writing and erasing are performed to a selective memory cell, a common nonselective voltage VWE/2 is applied to both a nonselective word line and a nonselective bit line not connected to the selective memory cell.