INTEGRATED CIRCUIT WITH LEAKAGE CONTROL AND METHOD FOR LEAKAGE CONTROL

The present invention relates to integrated circuit with reduced leakage power and in particular to a methodology for retaining an operational state of at least a part of the integrated circuit during the part is in standby/low power mode. In detail, the inventive methodology is based on the use of scan chains being implemented in the integrated circuit for production testing purposes. Via the scan chains circuit-internal state-variable memory element contents is read out and/or written in such that operational state of for instance a specific part (power domain) of the integrated circuit may be captured on the basis of the circuit internal contents, retained in an adequately provided data storage and afterwards scanned in the specific part of the integrated circuit to restore the operational state thereof.