METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT HAVING A BARRIER-LINED OPENING

A semiconductor component (10) having a metallization system that includes a thin conformal multi-layer barrier structure (60) and a method for manufacturing the semiconductor component (10). A layer of dielectric material (30, 34) is formed over a lower level interconnect. A hardmask (36) is formed...

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Bibliographische Detailangaben
Hauptverfasser:	WANG PIN CHIN CONNIE, HUANG RICHARD J
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	A semiconductor component (10) having a metallization system that includes a thin conformal multi-layer barrier structure (60) and a method for manufacturing the semiconductor component (10). A layer of dielectric material (30, 34) is formed over a lower level interconnect. A hardmask (36) is formed over the dielectric layer (30, 34) and an opening (50, 52, 54) is etched through the hardmask (36) into the dielectric layer (30, 34). The opening (50, 52, 54) is lined with a thin conformal multi-layer barrier (60) using atomic layer deposition. The multi-layer barrier lined opening is filled with an electrically conductive material (66) which is planarized.