METHOD FOR FORMING ELEMENT ISOLATION LAYER OF SEMICONDUCTOR DEVICE
A method of forming an isolation layer of a semiconductor device is provided to prevent a moat from being generated at a boundary between the isolation layer and an active region. A trench is formed in a silicon substrate(21) by performing etching using a pad nitride pattern and a pad oxide pattern(...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | A method of forming an isolation layer of a semiconductor device is provided to prevent a moat from being generated at a boundary between the isolation layer and an active region. A trench is formed in a silicon substrate(21) by performing etching using a pad nitride pattern and a pad oxide pattern(23) as an etching mask. An HDP(High Density Plasma) oxide layer(35) for filling completely the trench is formed thereon. A CMP(Chemical Mechanical Polishing) process is performed on a backside of the substrate. The pad nitride pattern is exposed to the outside by performing CMP on the HDP oxide layer. The remaining pad nitride and oxide patterns are removed therefrom. |
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