SYSTEM FOR DECODING COLUMN ADDRESS, IN WHICH TIMING MISMATCH IS SOLVED

PURPOSE: A system for decoding a column address is provided to generate the redundancy timing signal at the Y redundancy circuit by using the generated redundancy timing signal and latching the address. CONSTITUTION: A system for decoding a column address includes an address buffer(511), a command buffer(512), a clock buffer(513), an address latch unit(520), a command decoder(530), an Y-redundancy comparison unit(540), an Y-timing controller(550), a latch unit(560) and a free decoder(570). The address buffer(511) transmits the received address. The command buffer(512) transmits the received command signal. The clock buffer(513) transmits the received clocks as the inner clock signal. The address latch unit(520) latches by synchronizing with the inner clock signal. The command decoder(530) generates the inner command by synchronizing with the inner clock signal. The Y redundancy comparison unit(540) determines the redundancy address by comparing the received output signal of the Y address latch unit(520) with the Y address redundancy programmed in the inner fuse. The Y timing controller(550) controls the timing to the hit signal with simultaneously latching the output signal of the command decoder(530). The latch unit(560) receives the signal latched from the Y timing controller(550) and latches the output signal of the Y address latch unit(520). And, the free decoder(570) drives the pulse by receiving the output signal of the latch unit(560) and the output signal of the Y timing controller(550).