WIDE LOCK RANGE PLL-TYPE FREQUENCY SYNTHESIZER FOR ENHANCING PRECISION OF PHASE/FREQUENCY COMPARATOR WITHOUT DECREASING LOCKUP TIME AND METHOD FOR SELECTING OSCILLATION FREQUENCY

PURPOSE: A wide lock range PLL-type frequency synthesizer for enhancing precision of a phase/frequency comparator without decreasing lockup time and a method for selecting an oscillation frequency are provided to suppress the power consumption by improving a structure of the PLL-type frequency synthesizer. CONSTITUTION: A phase/frequency comparator(1) is used for receiving an input signal. A charge pump circuit(2) is connected to the phase/frequency comparator. A bias voltage source(12) is used for generating a bias voltage. A loop filter(3) is selectively connected to one of the charge pump circuit and the bias voltage to generate a control voltage. The charge pump circuit charges and discharges the loop filter in accordance with an output signal of the phase/frequency comparator and the bias voltage source applies the bias voltage to the loop filter. A voltage control oscillator block(4') is connected to the loop filter and includes a plurality of voltage controlled oscillators(41'-0, 41'-1, 41'-2, ..., 41'-(m-1)) controlled by the control voltage. A first frequency divider(51') is connected to the voltage controlled oscillator block. A second frequency divider(52') is connected to the first frequency divider and the phase/frequency comparator compares a phase of the input signal with a phase of an output signal of the second frequency divider. A selecting circuit(7',8') is connected to the first frequency divider and the voltage controlled oscillator block to select and activate only one of the voltage controlled oscillators. The selecting circuit is used for counting a number of output pulses of the first frequency divider within a predetermined number of output pulses of the input signal while applying the bias voltage to the loop filter. The one of the voltage controlled oscillators is selected so that the number of the output pulses of the first frequency divider is brought close to an optimum value.