Method of forming a dual damascene pattern in a semiconductor device
PURPOSE: A method for forming a dual damascene pattern of a semiconductor device is provided to be capable of easily forming a via hole though aspect ratio is increased, improving etching profile, and preventing the generation of misalignment. CONSTITUTION: The first insulating layer(12) is formed o...
Gespeichert in:
1. Verfasser: | |
---|---|
Format: | Patent |
Sprache: | eng ; kor |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | PURPOSE: A method for forming a dual damascene pattern of a semiconductor device is provided to be capable of easily forming a via hole though aspect ratio is increased, improving etching profile, and preventing the generation of misalignment. CONSTITUTION: The first insulating layer(12) is formed on a semiconductor substrate(11) having a predetermined structure. A via hole(15) is formed at the predetermined portion of the first insulating layer. The second insulating layer(16) is formed on the first insulating layer. At this time, voids is generated at the via hole(15). A trench(19) is formed at the second insulating layer(16) for opening the upper portion of the via hole(15). At this time, a dual damascene pattern(100) made of the trench(19) and via hole(15), is completed.
본 발명은 반도체 소자의 듀얼 다마신 패턴 형성 방법에 관한 것으로, 하부 절연층에 먼저 비아홀을 형성하고 상부 절연층을 형성하면서 비아홀에 보이드를 발생시킨 후 상부 절연층에 트렌치를 형성하면서 비아홀의 상부를 개방시켜 트렌치와 비아로 이루어진 듀얼 다마신 패턴을 형성하므로써, 종횡비(Aspect ratio)의 증가에 따른 비아홀 형성의 어려움을 해소하고 식각 프로파일을 향상시키며, 정렬 오차가 발생되는 것을 방지하여 공정의 신뢰성을 향상시킬 수 있는 반도체 소자의 듀얼 다마신 패턴 형성 방법이 개시된다. |
---|