Method of manufacturing a embeded memory cell

PURPOSE: A method for fabricating an embedded memory device is provided to reduce a leakage current and power consumption by making silicide not formed in a diffusion region in a cell region. CONSTITUTION: An isolation layer(12) is formed on a semiconductor substrate(11) to define a logic region and the cell region. A polysilicon layer and a nitride layer(18) are formed on the resultant structure including the isolation layer. The polysilicon layer and the nitride layer are patterned to form the first gate electrode(15) in the logic region and the second gate electrode(16) in the cell region. After a spacer is formed on the sidewall of the first and second gate electrodes, the diffusion region(20) is formed in the semiconductor substrate. After a silicide barrier is formed in the cell region, the first silicide(22) is formed in the logic region of the semiconductor substrate. The silicide barrier in the cell region is removed. An insulation layer is formed on the resultant structure. A planarization process is performed to expose the nitride layer. The nitride layer is removed to form a groove. The second silicide(24) is formed in the groove. 본 발명은 임베디드 메모리 소자 제조 방법에 관한 것으로, 로직 영역의 확산 영역에만 먼저 선택적으로 실리사이드를 형성한 후 별도의 공정으로 전체 게이트에 실리사이드를 형성함으로써 메모리 셀 영역의 확산영역에는 실리사이드를 형성시키지 않음으로써 누설 전류를 줄일 수 있는 임베디드 메모리 소자 제조 방법을 제공한다.