Charge Pump Circuit for PLL

PURPOSE: A charge pump circuit for a phase locked loop(PLL) is provided, which solves a mismatch problem of an up/down current and a feed-through of an up/down input signal to an output voltage at the same time. CONSTITUTION: A reference voltage is applied to a gate of the first transistor(M1). A source of the second transistor(M2) is connected to a source of the first transistor in common, and the first control voltage is applied to a gate of the second transistor, and a power supply voltage is applied to a drain of the second transistor. The reference voltage is applied to a data of the third transistor(M3). In the fourth transistor(M4), a source is connected to a source of the third transistor in common and the second control voltage is applied to a gate and the power supply voltage is applied to a drain. In the fifth transistor(M5), a drain is connected to a drain of the first transistor and its drain and a gate are connected in common and the power supply voltage is applied to a source. In the sixth transistor(M6), a drain is connected to the drain of the third transistor, and the drain and a gate are connected in common, and the power supply voltage is applied to the source. In the seventh transistor(M7), a gate is connected to the gate of the fifth transistor and the power supply voltage is applied to a source. In the eighth transistor(M8), a gate is connected to the gate of the sixth transistor and the power supply voltage is applied to a source. In the ninth transistor(M9), a drain is connected to the source of the eighth transistor, and a source is grounded and a gate and the drain are connected in common. The first current source is connected between a common source of the first and the second transistor and a ground. And the second current source is connected between a common source of the third and the fourth transistor and the ground. And an output port for forming a charging/discharging path of a charging device is formed at a connection point of the drains of the seventh and the tenth transistor(M10). 본 발명은 위상 동기 루프용 충전 펌프의 성능에 있어 가중 중요한 두가지 요인인 업/다운 전류(up/down current)의 비정합(mismatch) 문제 및 업/다운 입력신호가 출력 전압으로 관통(feed-through)하는 문제를 동시에 개선하기 위한, 위상 동기 루프용 충전 펌프 회로에 관한 것으로서, 직류(DC) 기준 전압을 이용한 차동 구조의 스위치(M1과 M2, M3과 M4)를 충전 펌프에 이용함으로써 입력 신호의 출력으로의 관통(feed-through)을 없앨 뿐만 아니라, 피드백을 이용한 레플리카 바이어싱(replica biasing)을 새롭게 적용하여 업/다운(up/down) 전류의 비정합(mismatch)이 넓은 출력 전압 범위에서 제거되도록 한다.