SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
PURPOSE: A semiconductor memory device and a fabricating method thereof are provided to prevent the characteristic of a capacitive insulation film from being deteriorated by exposing an upper electrode to a reducing atmosphere. CONSTITUTION: A bit line(21a) connected to a bit line plug and a local i...
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| creator | OGAWA HISASHI TSUZUMITANI AKIHIKO MORI YOSHIHIRO |
| description | PURPOSE: A semiconductor memory device and a fabricating method thereof are provided to prevent the characteristic of a capacitive insulation film from being deteriorated by exposing an upper electrode to a reducing atmosphere. CONSTITUTION: A bit line(21a) connected to a bit line plug and a local interconnection(21b) are formed on the first interlayer insulation film. A contact is not formed on a Pt film(35) constituting the upper electrode, and a dummy lower electrode(33b) is in direct contact with a dummy barrier metal(32b). The upper electrode is connected to an upper layer interconnection(Cu interconnection)(42) by the dummy lower electrode, a dummy cell plug(30b) and the local interconnection.
본 발명은 메탈 상부전극을 노출시키는 것에 의한 용량절연막의 특성열화를 방지한 반도체기억장치 및 그 제조방법을 제공하기 위한 것으로, 반도체기억장치인 DRAM의 메모리셀에 있어서, 제 1 층간절연막(18) 상에는 비트선 플러그(20b)에 접속되는 비트선(21a)과 국소배선(21b)이 설치되어 있다. 상부전극(35a)을 구성하는 Pt막(35) 상에 컨택트가 설치되어 있지 않고, 더미하부전극(33b)은 더미배리어메탈(32b)과 직접 접하고 있다. 즉, 더미하부전극(33b), 더미셀 플러그(30) 및 국소배선(21b)에 의해서 상부전극(35a)이 상층배선(Cu 배선(42))에 접속되어 있다. Pt막(35)이 환원성 분위기에 노출되지 않으므로, 용량절연막(34a)의 특성열화를 방지할 수 있다. |
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본 발명은 메탈 상부전극을 노출시키는 것에 의한 용량절연막의 특성열화를 방지한 반도체기억장치 및 그 제조방법을 제공하기 위한 것으로, 반도체기억장치인 DRAM의 메모리셀에 있어서, 제 1 층간절연막(18) 상에는 비트선 플러그(20b)에 접속되는 비트선(21a)과 국소배선(21b)이 설치되어 있다. 상부전극(35a)을 구성하는 Pt막(35) 상에 컨택트가 설치되어 있지 않고, 더미하부전극(33b)은 더미배리어메탈(32b)과 직접 접하고 있다. 즉, 더미하부전극(33b), 더미셀 플러그(30) 및 국소배선(21b)에 의해서 상부전극(35a)이 상층배선(Cu 배선(42))에 접속되어 있다. Pt막(35)이 환원성 분위기에 노출되지 않으므로, 용량절연막(34a)의 특성열화를 방지할 수 있다.</description><edition>7</edition><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20030129&DB=EPODOC&CC=KR&NR=20030009207A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20030129&DB=EPODOC&CC=KR&NR=20030009207A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OGAWA HISASHI</creatorcontrib><creatorcontrib>TSUZUMITANI AKIHIKO</creatorcontrib><creatorcontrib>MORI YOSHIHIRO</creatorcontrib><title>SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME</title><description>PURPOSE: A semiconductor memory device and a fabricating method thereof are provided to prevent the characteristic of a capacitive insulation film from being deteriorated by exposing an upper electrode to a reducing atmosphere. CONSTITUTION: A bit line(21a) connected to a bit line plug and a local interconnection(21b) are formed on the first interlayer insulation film. A contact is not formed on a Pt film(35) constituting the upper electrode, and a dummy lower electrode(33b) is in direct contact with a dummy barrier metal(32b). The upper electrode is connected to an upper layer interconnection(Cu interconnection)(42) by the dummy lower electrode, a dummy cell plug(30b) and the local interconnection.
본 발명은 메탈 상부전극을 노출시키는 것에 의한 용량절연막의 특성열화를 방지한 반도체기억장치 및 그 제조방법을 제공하기 위한 것으로, 반도체기억장치인 DRAM의 메모리셀에 있어서, 제 1 층간절연막(18) 상에는 비트선 플러그(20b)에 접속되는 비트선(21a)과 국소배선(21b)이 설치되어 있다. 상부전극(35a)을 구성하는 Pt막(35) 상에 컨택트가 설치되어 있지 않고, 더미하부전극(33b)은 더미배리어메탈(32b)과 직접 접하고 있다. 즉, 더미하부전극(33b), 더미셀 플러그(30) 및 국소배선(21b)에 의해서 상부전극(35a)이 상층배선(Cu 배선(42))에 접속되어 있다. Pt막(35)이 환원성 분위기에 노출되지 않으므로, 용량절연막(34a)의 특성열화를 방지할 수 있다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAPdvX1dPb3cwl1DvEPUvB19fUPilRwcQ3zdHZVcPRzAYqEePi7KLgBJd0cnYI8nR1DPP3cFUI8XBWCHX1deRhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJvHeQkYGBsYGBgaWRgbmjMXGqABeiKvQ</recordid><startdate>20030129</startdate><enddate>20030129</enddate><creator>OGAWA HISASHI</creator><creator>TSUZUMITANI AKIHIKO</creator><creator>MORI YOSHIHIRO</creator><scope>EVB</scope></search><sort><creationdate>20030129</creationdate><title>SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME</title><author>OGAWA HISASHI ; TSUZUMITANI AKIHIKO ; MORI YOSHIHIRO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20030009207A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2003</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>OGAWA HISASHI</creatorcontrib><creatorcontrib>TSUZUMITANI AKIHIKO</creatorcontrib><creatorcontrib>MORI YOSHIHIRO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OGAWA HISASHI</au><au>TSUZUMITANI AKIHIKO</au><au>MORI YOSHIHIRO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME</title><date>2003-01-29</date><risdate>2003</risdate><abstract>PURPOSE: A semiconductor memory device and a fabricating method thereof are provided to prevent the characteristic of a capacitive insulation film from being deteriorated by exposing an upper electrode to a reducing atmosphere. CONSTITUTION: A bit line(21a) connected to a bit line plug and a local interconnection(21b) are formed on the first interlayer insulation film. A contact is not formed on a Pt film(35) constituting the upper electrode, and a dummy lower electrode(33b) is in direct contact with a dummy barrier metal(32b). The upper electrode is connected to an upper layer interconnection(Cu interconnection)(42) by the dummy lower electrode, a dummy cell plug(30b) and the local interconnection.
본 발명은 메탈 상부전극을 노출시키는 것에 의한 용량절연막의 특성열화를 방지한 반도체기억장치 및 그 제조방법을 제공하기 위한 것으로, 반도체기억장치인 DRAM의 메모리셀에 있어서, 제 1 층간절연막(18) 상에는 비트선 플러그(20b)에 접속되는 비트선(21a)과 국소배선(21b)이 설치되어 있다. 상부전극(35a)을 구성하는 Pt막(35) 상에 컨택트가 설치되어 있지 않고, 더미하부전극(33b)은 더미배리어메탈(32b)과 직접 접하고 있다. 즉, 더미하부전극(33b), 더미셀 플러그(30) 및 국소배선(21b)에 의해서 상부전극(35a)이 상층배선(Cu 배선(42))에 접속되어 있다. Pt막(35)이 환원성 분위기에 노출되지 않으므로, 용량절연막(34a)의 특성열화를 방지할 수 있다.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| title | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME |
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