SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

PURPOSE: A semiconductor memory device and a fabricating method thereof are provided to prevent the characteristic of a capacitive insulation film from being deteriorated by exposing an upper electrode to a reducing atmosphere. CONSTITUTION: A bit line(21a) connected to a bit line plug and a local i...

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Bibliographische Detailangaben
Hauptverfasser:	OGAWA HISASHI, TSUZUMITANI AKIHIKO, MORI YOSHIHIRO
Format:	Patent
Sprache:	eng ; kor
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	PURPOSE: A semiconductor memory device and a fabricating method thereof are provided to prevent the characteristic of a capacitive insulation film from being deteriorated by exposing an upper electrode to a reducing atmosphere. CONSTITUTION: A bit line(21a) connected to a bit line plug and a local interconnection(21b) are formed on the first interlayer insulation film. A contact is not formed on a Pt film(35) constituting the upper electrode, and a dummy lower electrode(33b) is in direct contact with a dummy barrier metal(32b). The upper electrode is connected to an upper layer interconnection(Cu interconnection)(42) by the dummy lower electrode, a dummy cell plug(30b) and the local interconnection. 본 발명은 메탈 상부전극을 노출시키는 것에 의한 용량절연막의 특성열화를 방지한 반도체기억장치 및 그 제조방법을 제공하기 위한 것으로, 반도체기억장치인 DRAM의 메모리셀에 있어서, 제 1 층간절연막(18) 상에는 비트선 플러그(20b)에 접속되는 비트선(21a)과 국소배선(21b)이 설치되어 있다. 상부전극(35a)을 구성하는 Pt막(35) 상에 컨택트가 설치되어 있지 않고, 더미하부전극(33b)은 더미배리어메탈(32b)과 직접 접하고 있다. 즉, 더미하부전극(33b), 더미셀 플러그(30) 및 국소배선(21b)에 의해서 상부전극(35a)이 상층배선(Cu 배선(42))에 접속되어 있다. Pt막(35)이 환원성 분위기에 노출되지 않으므로, 용량절연막(34a)의 특성열화를 방지할 수 있다.