Method for forming a metal line

PURPOSE: A method for fabricating a metal interconnection is provided to prevent a contact area between a tungsten plug and a metal interconnection from increasing so that via resistance is reduced, by forming a tungsten spacer on the sidewall of the metal interconnection. CONSTITUTION: The metal in...

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Bibliographische Detailangaben
1. Verfasser: JUNG, JONG YEOL
Format: Patent
Sprache:eng ; kor
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Beschreibung
Zusammenfassung:PURPOSE: A method for fabricating a metal interconnection is provided to prevent a contact area between a tungsten plug and a metal interconnection from increasing so that via resistance is reduced, by forming a tungsten spacer on the sidewall of the metal interconnection. CONSTITUTION: The metal interconnection(33) is formed on a substrate insulated by an insulation layer, in which the substrate is electrically connected to the metal interconnection. A conductive layer spacer is formed on the insulated substrate(31) at both sides of the metal interconnection. A flat interlayer dielectric(35) is formed on the entire surface including the conductive layer spacer. The interlayer dielectric is selectively etched to form a via hole by using a via contact mask. A plug filling the via hole is formed. 본 발명은 금속 배선 형성 방법에 관한 것으로, 특히 금속 배선 측벽에 텅스텐(W) 스페이서(Spacer)를 형성하므로, 비아홀 형성 공정 시 미스얼라인(Misalign)이 발생하여도 후속 공정으로 상기 비아홀에 형성되는 텅스텐 플러그와 금속 배선간의 접촉 면적 감소를 방지하여 비아 저항을 감소시키고 비아홀 형성의 공정 마진(Margin)을 확보하여 소자의 특성을 향상시키는 특징이 있다.