METHOD FOR FORMING DUMMY PATTERN FOR GATE POLY

PURPOSE: A method for forming a dummy pattern for gate poly is provided to improve a current characteristic and a voltage characteristic by compensating ADI(After Developing Inspection) critical dimension and ACI(After Cleaning Inspection) critical dimension. CONSTITUTION: A gate poly dummy pattern(...

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Bibliographische Detailangaben
Hauptverfasser:	YOO, JAE CHEOL, WANG, SEON JONG
Format:	Patent
Sprache:	eng ; kor
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	PURPOSE: A method for forming a dummy pattern for gate poly is provided to improve a current characteristic and a voltage characteristic by compensating ADI(After Developing Inspection) critical dimension and ACI(After Cleaning Inspection) critical dimension. CONSTITUTION: A gate poly dummy pattern(130) is formed around an active pattern(120). The gate poly dummy pattern(130) is formed with the first gate poly dummy pattern(132) and the second gate poly dummy pattern(135). The first gate poly dummy pattern(132) is formed by adding a gate poly to an active region. An interval between the first gate poly dummy pattern(132) and the first gate poly dummy pattern(132) is 0.4 to 0.5 micro meter. Each of the first gate poly dummy pattern(132) has 1x1 micro meter. The interval between the first gate poly dummy pattern(132) and the second gate poly dummy pattern(135) is more than 0.5 micro meter. Each of the second gate poly dummy pattern(135) has 4x4 micro meter or 3x3 micro meter.