DATA OUTPUT BUFFER CONTROL CIRCUIT

PURPOSE: A data output buffer control circuit is provided, which improves a yield by stabilizing an operation of the circuit by controlling a time(tAC) from when a data hold time(tOH) and a clock signal(clock) are applied until effective data are output at random. CONSTITUTION: A control signal generation unit generates a number of control signals by decoding an output signal of a number of fuse box parts having fuses. A data output control signal generation unit controls a timing by controlling a delay of the data output control signal generated from a clock by a number of clock signals from the control signal generation unit. And a data output enable signal generation unit controls a timing by controlling a delay of the data output enable signal generated from a clock by a number of control signals generated from the control signal generation unit. The control signal generation unit comprises the first and the second fuse box part(50,60) outputting a 'high' or 'low' level signal by a connection state of the fuse, and a decoding circuit part outputting control signals by decoding the output signals of the first and the second fuse box part.