FAULTY REPAIR CONTROL CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE

PURPOSE: A faulty repair control circuit in a semiconductor memory device is provided to be capable of repairing faulty cells detected before an EDS(Electrical Die Sorting) test as well as repairing faulty cells detected during the EDS test. CONSTITUTION: The control circuit comprises a faulty repai...

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Bibliographische Detailangaben
Hauptverfasser: KIM, BYEONG SUL, SONG, YUN GYU
Format: Patent
Sprache:eng ; kor
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Beschreibung
Zusammenfassung:PURPOSE: A faulty repair control circuit in a semiconductor memory device is provided to be capable of repairing faulty cells detected before an EDS(Electrical Die Sorting) test as well as repairing faulty cells detected during the EDS test. CONSTITUTION: The control circuit comprises a faulty repair main controller(100), a faulty repair sub controller(110) and row/column redundancy controllers(120-160,165-180). The row redundancy controllers(120-160) repair faulty cells present in one row segment. The column redundancy controllers(165-180) repair faulty cells present in one column segment. The faulty repair main controller(100) is connected in parallel to a plurality of row and column redundancy controllers assigned to a plurality of row and column segments.