METHOD AND STRUCTURE OF COLUMN INTERCONNECT
PURPOSE: A method and structure of column interconnection are provided to improve adhesive strength between the last metal layer and a dielectric adjacent to it. CONSTITUTION: A semiconductor chip includes a last metallic layer(LD,11) and a second last metallic layer(LM-1,13), a conductive via(12) c...
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| creator | BERGMAN-REUTER BETTE L FEENEY PAUL M PREVITI-KELLY ROSEMARY A STAMPER ANTHONY K ELLIS-MONAGHAN JOHN J GEFFKEN ROBERT M LANDIS HOWARD S RUTTEN MATTHEW J YANKEE SALLY J |
| description | PURPOSE: A method and structure of column interconnection are provided to improve adhesive strength between the last metal layer and a dielectric adjacent to it. CONSTITUTION: A semiconductor chip includes a last metallic layer(LD,11) and a second last metallic layer(LM-1,13), a conductive via(12) connected with two metal layers(11,13), an interlayer dielectric(14). A support structure includes a protection cap(10) on the interlayer dielectric(14) by a CVD. The thickness of the cap is about 1-20 micrometer. The support structure includes a patterned metal layer insulated by a rigid dielectric.
복수개의 상호접속 금속층과, 상호접속 금속 위의 적어도 하나의 변형가능한 유전체 물질과, 적어도 하나의 입력/출력 접합 패드와, 패드를 지지하는 실질적으로 단단한 유전체를 포함하며 변형가능한 유전체 물질의 파쇄를 방지하는 지지 구조물을 포함하는 반도체 칩의 구조 및 방법이 제공된다. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20010091908A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20010091908A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20010091908A3</originalsourceid><addsrcrecordid>eNrjZND2dQ3x8HdRcPRzUQgOCQp1DgkNclXwd1Nw9vcJ9fVT8PQLcQ1y9vfzc3UO4WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8d5BRgYGhgYGloaWBhaOxsSpAgAQQCXe</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD AND STRUCTURE OF COLUMN INTERCONNECT</title><source>esp@cenet</source><creator>BERGMAN-REUTER BETTE L ; FEENEY PAUL M ; PREVITI-KELLY ROSEMARY A ; STAMPER ANTHONY K ; ELLIS-MONAGHAN JOHN J ; GEFFKEN ROBERT M ; LANDIS HOWARD S ; RUTTEN MATTHEW J ; YANKEE SALLY J</creator><creatorcontrib>BERGMAN-REUTER BETTE L ; FEENEY PAUL M ; PREVITI-KELLY ROSEMARY A ; STAMPER ANTHONY K ; ELLIS-MONAGHAN JOHN J ; GEFFKEN ROBERT M ; LANDIS HOWARD S ; RUTTEN MATTHEW J ; YANKEE SALLY J</creatorcontrib><description>PURPOSE: A method and structure of column interconnection are provided to improve adhesive strength between the last metal layer and a dielectric adjacent to it. CONSTITUTION: A semiconductor chip includes a last metallic layer(LD,11) and a second last metallic layer(LM-1,13), a conductive via(12) connected with two metal layers(11,13), an interlayer dielectric(14). A support structure includes a protection cap(10) on the interlayer dielectric(14) by a CVD. The thickness of the cap is about 1-20 micrometer. The support structure includes a patterned metal layer insulated by a rigid dielectric.
복수개의 상호접속 금속층과, 상호접속 금속 위의 적어도 하나의 변형가능한 유전체 물질과, 적어도 하나의 입력/출력 접합 패드와, 패드를 지지하는 실질적으로 단단한 유전체를 포함하며 변형가능한 유전체 물질의 파쇄를 방지하는 지지 구조물을 포함하는 반도체 칩의 구조 및 방법이 제공된다.</description><edition>7</edition><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20011023&DB=EPODOC&CC=KR&NR=20010091908A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20011023&DB=EPODOC&CC=KR&NR=20010091908A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BERGMAN-REUTER BETTE L</creatorcontrib><creatorcontrib>FEENEY PAUL M</creatorcontrib><creatorcontrib>PREVITI-KELLY ROSEMARY A</creatorcontrib><creatorcontrib>STAMPER ANTHONY K</creatorcontrib><creatorcontrib>ELLIS-MONAGHAN JOHN J</creatorcontrib><creatorcontrib>GEFFKEN ROBERT M</creatorcontrib><creatorcontrib>LANDIS HOWARD S</creatorcontrib><creatorcontrib>RUTTEN MATTHEW J</creatorcontrib><creatorcontrib>YANKEE SALLY J</creatorcontrib><title>METHOD AND STRUCTURE OF COLUMN INTERCONNECT</title><description>PURPOSE: A method and structure of column interconnection are provided to improve adhesive strength between the last metal layer and a dielectric adjacent to it. CONSTITUTION: A semiconductor chip includes a last metallic layer(LD,11) and a second last metallic layer(LM-1,13), a conductive via(12) connected with two metal layers(11,13), an interlayer dielectric(14). A support structure includes a protection cap(10) on the interlayer dielectric(14) by a CVD. The thickness of the cap is about 1-20 micrometer. The support structure includes a patterned metal layer insulated by a rigid dielectric.
복수개의 상호접속 금속층과, 상호접속 금속 위의 적어도 하나의 변형가능한 유전체 물질과, 적어도 하나의 입력/출력 접합 패드와, 패드를 지지하는 실질적으로 단단한 유전체를 포함하며 변형가능한 유전체 물질의 파쇄를 방지하는 지지 구조물을 포함하는 반도체 칩의 구조 및 방법이 제공된다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZND2dQ3x8HdRcPRzUQgOCQp1DgkNclXwd1Nw9vcJ9fVT8PQLcQ1y9vfzc3UO4WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8d5BRgYGhgYGloaWBhaOxsSpAgAQQCXe</recordid><startdate>20011023</startdate><enddate>20011023</enddate><creator>BERGMAN-REUTER BETTE L</creator><creator>FEENEY PAUL M</creator><creator>PREVITI-KELLY ROSEMARY A</creator><creator>STAMPER ANTHONY K</creator><creator>ELLIS-MONAGHAN JOHN J</creator><creator>GEFFKEN ROBERT M</creator><creator>LANDIS HOWARD S</creator><creator>RUTTEN MATTHEW J</creator><creator>YANKEE SALLY J</creator><scope>EVB</scope></search><sort><creationdate>20011023</creationdate><title>METHOD AND STRUCTURE OF COLUMN INTERCONNECT</title><author>BERGMAN-REUTER BETTE L ; FEENEY PAUL M ; PREVITI-KELLY ROSEMARY A ; STAMPER ANTHONY K ; ELLIS-MONAGHAN JOHN J ; GEFFKEN ROBERT M ; LANDIS HOWARD S ; RUTTEN MATTHEW J ; YANKEE SALLY J</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20010091908A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2001</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>BERGMAN-REUTER BETTE L</creatorcontrib><creatorcontrib>FEENEY PAUL M</creatorcontrib><creatorcontrib>PREVITI-KELLY ROSEMARY A</creatorcontrib><creatorcontrib>STAMPER ANTHONY K</creatorcontrib><creatorcontrib>ELLIS-MONAGHAN JOHN J</creatorcontrib><creatorcontrib>GEFFKEN ROBERT M</creatorcontrib><creatorcontrib>LANDIS HOWARD S</creatorcontrib><creatorcontrib>RUTTEN MATTHEW J</creatorcontrib><creatorcontrib>YANKEE SALLY J</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BERGMAN-REUTER BETTE L</au><au>FEENEY PAUL M</au><au>PREVITI-KELLY ROSEMARY A</au><au>STAMPER ANTHONY K</au><au>ELLIS-MONAGHAN JOHN J</au><au>GEFFKEN ROBERT M</au><au>LANDIS HOWARD S</au><au>RUTTEN MATTHEW J</au><au>YANKEE SALLY J</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD AND STRUCTURE OF COLUMN INTERCONNECT</title><date>2001-10-23</date><risdate>2001</risdate><abstract>PURPOSE: A method and structure of column interconnection are provided to improve adhesive strength between the last metal layer and a dielectric adjacent to it. CONSTITUTION: A semiconductor chip includes a last metallic layer(LD,11) and a second last metallic layer(LM-1,13), a conductive via(12) connected with two metal layers(11,13), an interlayer dielectric(14). A support structure includes a protection cap(10) on the interlayer dielectric(14) by a CVD. The thickness of the cap is about 1-20 micrometer. The support structure includes a patterned metal layer insulated by a rigid dielectric.
복수개의 상호접속 금속층과, 상호접속 금속 위의 적어도 하나의 변형가능한 유전체 물질과, 적어도 하나의 입력/출력 접합 패드와, 패드를 지지하는 실질적으로 단단한 유전체를 포함하며 변형가능한 유전체 물질의 파쇄를 방지하는 지지 구조물을 포함하는 반도체 칩의 구조 및 방법이 제공된다.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | METHOD AND STRUCTURE OF COLUMN INTERCONNECT |
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