METHOD FOR FABRICATING OF SEMICONDUCTOR DEVICE
PURPOSE: A manufacturing method of a semiconductor device is to form a gate electrode with a low resistance, without causing damage to a gate oxide, and to simplify a manufacturing process. CONSTITUTION: A gate oxide(32) is formed on a semiconductor substrate(31). The first metal layer(33) composed...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng ; kor |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | JI, SEUNG HEON |
| description | PURPOSE: A manufacturing method of a semiconductor device is to form a gate electrode with a low resistance, without causing damage to a gate oxide, and to simplify a manufacturing process. CONSTITUTION: A gate oxide(32) is formed on a semiconductor substrate(31). The first metal layer(33) composed of Ti/TiN is deposited on the gate oxide, and then the second metal layer(35) composed of W is deposited thereon. An insulating layer is then deposited on the second metal layer. The insulating layer is anisotropically etched using a patterned photoresist as a mask to form a capping insulating layer(36a) on the second metal layer. The second and the first metal layers are sequentially etched using the capping insulating layer as a mask to form a gate electrode.
공정을 단순화 시키면서 게이트의 저항을 줄이기에 알맞은 반도체소자의 제조방법을 제공하기 위한 것으로써, 이와 같은 목적을 달성하기 위한 반도체소자의 제조방법은 반도체기판에 게이트절연막을 형성하는 공정, 상기 게이트절연막상에 제 1, 제 2 메탈층을 차례로 형성하는 공정, 상기 제 2 메탈층상에 절연막을 형성하는 공정, 상기 절연막을 식각하여 게이트 형성 부분상측의 상기 제 2 메탈층상에 캡절연막을 형성하는 공정, 상기 캡절연막을 마스크로 상기 제 2 메탈층과 제 1 메탈층을 차례로 식각하여 게이트전극을 형성하는 공정을 포함함을 특징으로 한다. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20010082903A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20010082903A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20010082903A3</originalsourceid><addsrcrecordid>eNrjZNDzdQ3x8HdRcPMPUnBzdArydHYM8fRzV_B3Uwh29fV09vdzCXUOAUq6uIZ5OrvyMLCmJeYUp_JCaW4GZTfXEGcP3dSC_PjU4oLE5NS81JJ47yAjAwNDAwMLI0sDY0dj4lQBAGZOJmk</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD FOR FABRICATING OF SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>JI, SEUNG HEON</creator><creatorcontrib>JI, SEUNG HEON</creatorcontrib><description>PURPOSE: A manufacturing method of a semiconductor device is to form a gate electrode with a low resistance, without causing damage to a gate oxide, and to simplify a manufacturing process. CONSTITUTION: A gate oxide(32) is formed on a semiconductor substrate(31). The first metal layer(33) composed of Ti/TiN is deposited on the gate oxide, and then the second metal layer(35) composed of W is deposited thereon. An insulating layer is then deposited on the second metal layer. The insulating layer is anisotropically etched using a patterned photoresist as a mask to form a capping insulating layer(36a) on the second metal layer. The second and the first metal layers are sequentially etched using the capping insulating layer as a mask to form a gate electrode.
공정을 단순화 시키면서 게이트의 저항을 줄이기에 알맞은 반도체소자의 제조방법을 제공하기 위한 것으로써, 이와 같은 목적을 달성하기 위한 반도체소자의 제조방법은 반도체기판에 게이트절연막을 형성하는 공정, 상기 게이트절연막상에 제 1, 제 2 메탈층을 차례로 형성하는 공정, 상기 제 2 메탈층상에 절연막을 형성하는 공정, 상기 절연막을 식각하여 게이트 형성 부분상측의 상기 제 2 메탈층상에 캡절연막을 형성하는 공정, 상기 캡절연막을 마스크로 상기 제 2 메탈층과 제 1 메탈층을 차례로 식각하여 게이트전극을 형성하는 공정을 포함함을 특징으로 한다.</description><edition>7</edition><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010831&DB=EPODOC&CC=KR&NR=20010082903A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010831&DB=EPODOC&CC=KR&NR=20010082903A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JI, SEUNG HEON</creatorcontrib><title>METHOD FOR FABRICATING OF SEMICONDUCTOR DEVICE</title><description>PURPOSE: A manufacturing method of a semiconductor device is to form a gate electrode with a low resistance, without causing damage to a gate oxide, and to simplify a manufacturing process. CONSTITUTION: A gate oxide(32) is formed on a semiconductor substrate(31). The first metal layer(33) composed of Ti/TiN is deposited on the gate oxide, and then the second metal layer(35) composed of W is deposited thereon. An insulating layer is then deposited on the second metal layer. The insulating layer is anisotropically etched using a patterned photoresist as a mask to form a capping insulating layer(36a) on the second metal layer. The second and the first metal layers are sequentially etched using the capping insulating layer as a mask to form a gate electrode.
공정을 단순화 시키면서 게이트의 저항을 줄이기에 알맞은 반도체소자의 제조방법을 제공하기 위한 것으로써, 이와 같은 목적을 달성하기 위한 반도체소자의 제조방법은 반도체기판에 게이트절연막을 형성하는 공정, 상기 게이트절연막상에 제 1, 제 2 메탈층을 차례로 형성하는 공정, 상기 제 2 메탈층상에 절연막을 형성하는 공정, 상기 절연막을 식각하여 게이트 형성 부분상측의 상기 제 2 메탈층상에 캡절연막을 형성하는 공정, 상기 캡절연막을 마스크로 상기 제 2 메탈층과 제 1 메탈층을 차례로 식각하여 게이트전극을 형성하는 공정을 포함함을 특징으로 한다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDzdQ3x8HdRcPMPUnBzdArydHYM8fRzV_B3Uwh29fV09vdzCXUOAUq6uIZ5OrvyMLCmJeYUp_JCaW4GZTfXEGcP3dSC_PjU4oLE5NS81JJ47yAjAwNDAwMLI0sDY0dj4lQBAGZOJmk</recordid><startdate>20010831</startdate><enddate>20010831</enddate><creator>JI, SEUNG HEON</creator><scope>EVB</scope></search><sort><creationdate>20010831</creationdate><title>METHOD FOR FABRICATING OF SEMICONDUCTOR DEVICE</title><author>JI, SEUNG HEON</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20010082903A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2001</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JI, SEUNG HEON</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JI, SEUNG HEON</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR FABRICATING OF SEMICONDUCTOR DEVICE</title><date>2001-08-31</date><risdate>2001</risdate><abstract>PURPOSE: A manufacturing method of a semiconductor device is to form a gate electrode with a low resistance, without causing damage to a gate oxide, and to simplify a manufacturing process. CONSTITUTION: A gate oxide(32) is formed on a semiconductor substrate(31). The first metal layer(33) composed of Ti/TiN is deposited on the gate oxide, and then the second metal layer(35) composed of W is deposited thereon. An insulating layer is then deposited on the second metal layer. The insulating layer is anisotropically etched using a patterned photoresist as a mask to form a capping insulating layer(36a) on the second metal layer. The second and the first metal layers are sequentially etched using the capping insulating layer as a mask to form a gate electrode.
공정을 단순화 시키면서 게이트의 저항을 줄이기에 알맞은 반도체소자의 제조방법을 제공하기 위한 것으로써, 이와 같은 목적을 달성하기 위한 반도체소자의 제조방법은 반도체기판에 게이트절연막을 형성하는 공정, 상기 게이트절연막상에 제 1, 제 2 메탈층을 차례로 형성하는 공정, 상기 제 2 메탈층상에 절연막을 형성하는 공정, 상기 절연막을 식각하여 게이트 형성 부분상측의 상기 제 2 메탈층상에 캡절연막을 형성하는 공정, 상기 캡절연막을 마스크로 상기 제 2 메탈층과 제 1 메탈층을 차례로 식각하여 게이트전극을 형성하는 공정을 포함함을 특징으로 한다.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; kor |
| recordid | cdi_epo_espacenet_KR20010082903A |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | METHOD FOR FABRICATING OF SEMICONDUCTOR DEVICE |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-29T06%3A30%3A37IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=JI,%20SEUNG%20HEON&rft.date=2001-08-31&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EKR20010082903A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |