DRAM HAVING A REDUCED CHIP SIZE

DRAM HAVING A REDUCED CHIP SIZE

PURPOSE: To provide a semiconductor memory device, with which flexibility in design is enlarged and an effective chip area can be reduced. CONSTITUTION: A memory cell plate couple, composed of two memory cell plates of different banks share an input/output amplifier 2, while assigning both I/O termi...

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Bibliographische Detailangaben
1. Verfasser: ORII YURIKO
Format: Patent
Sprache:eng ; kor
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Beschreibung
Zusammenfassung:PURPOSE: To provide a semiconductor memory device, with which flexibility in design is enlarged and an effective chip area can be reduced. CONSTITUTION: A memory cell plate couple, composed of two memory cell plates of different banks share an input/output amplifier 2, while assigning both I/O terminals in the same order. Memory cell plate versus 11 and 15, and between 13 and 17, 12 and 16, and 14 and 18 are respectively connected by correspondent input/output buses and respectively connected to a pad 1, to which I/O terminals are allocated in the state of shift, by correspondent input/output buses. DDR-SDRAM은 다수의 메모리 셀의 뱅크들을 가지며, 각각의 뱅크들은 동시에 선택적으로 활성화된다. 각 뱅크는 2개의 메모리 셀 플레이트(11, 12 ; 13, 14; 15, 16; 17, 18)를 포함하며, 각각의 플레이트는 나머지 뱅크 중 대응하는 메모리 셀 플레이트와 나란히 배치되어 I/O 증폭기(32) 및 전원선의 브랜치 라인(24)을 공유하는 메모리 셀 플레이트 쌍을 형성한다. I/O 증폭기(32)의 수와 브랜치 라인(24)의 폭은 메모리 셀 플레이트 쌍 양자가 동시에 활성화되지 않기 때문에 감소될 수 있다.