CIRCUIT FOR CONTROLLING THE SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE

PURPOSE: A circuit for controlling a sense amplifier is provided to reduce a signal transfer path and the number of gates necessary for consisting of the circuit by generating sense amp control signals by using sense amp enable bar signals. CONSTITUTION: A circuit for controlling a sense amplifier of a semiconductor memory device includes a first through seventh logic gates. The first logic gate(504) outputs logic 0 when at least one of input sense amp enable bar signals is logic 1. The second logic gate(508) outputs a first NMOS sense amp enable bar signal of high level when an output of the first logic gate is logic 0 and the sense amp enable bar signal is logic 1. The third logic gate(512) outputs a first PMOS sense amp enable bar signal of high level when at least one of an output of the first logic gate and the sense amp enable bar signal. The fourth logic gate outputs logic 1 when at least one of a plurality of mat selection bar signals is logic 0. The fifth logic gate outputs logic 1 when the first NMOS sense amp enable bar signal is logic 0 and an output of the fourth logic gate is logic 1. The sixth logic gate outputs logic 0 when the first PMOS sense amp enable bar signal is logic 1 and an output of the fourth logic gate is logic 1. The seventh logic gate outputs a second PMOS sense amp control signal of logic 1 when both outputs of the fifth and sixth logic gates are logic 1.