CONTROL CIRCUIT FOR DATA OUTPUT BUFFER HAVING SMALL CHIP AREA AND LOW POWER CONSUMPTION AND SYNCHRONOUS DRAM OF DUAL DATA RATE WITH SAME

PURPOSE: A control circuit for a data output buffer is provided to reduce the area of a chip and power consumption by not requiring a large number of bus lines. CONSTITUTION: A COSR becomes high by a read command for enabling latency into high after delaying one clock. A PTRSTB becomes low for turning on a transferring gate(6) by using a CL2 while turning off a transferring gate(7,8). Therefore, when CLK_F becomes high, a PTRST is high for operating a data output buffer(1115). After completing a burst reading, the latency is disabled into low after delaying one clock. Thus, the PTRSTB becomes high. When the CLK_F becomes high, the transferring gate(6) is turned on for disabling the PTRST into low. Therefore, the operation of the data output buffer is stopped. Herein, a control circuit for the data output buffer uses one first latency signal, one delay signal for the first latency signal, one second latency signal, one buffered first latency signal, and one buffered second latency signal. Thus, the control circuit contains simple structure while reducing a chip area and electricity consumption.