MULTI SYNCHRONIZATION DEFLECTION CIRCUIT
PURPOSE: A multi synchronization deflection circuit is provided to prevent the deflection malfunction due to an equalization pulse during a vertical synchronization period. CONSTITUTION: A multi synchronization deflection circuit includes a compared pulse generator(120), an equalization pulse remove...
Gespeichert in:
1. Verfasser: | |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | PURPOSE: A multi synchronization deflection circuit is provided to prevent the deflection malfunction due to an equalization pulse during a vertical synchronization period. CONSTITUTION: A multi synchronization deflection circuit includes a compared pulse generator(120), an equalization pulse remover(130), first through Nth deflectors(160A,160B-160N), a switch(150), and a synchronous mode discriminator(140). When a horizontal synchronous pulse is applied, the compared pulse generator(120) generates a pulse with the phase and frequency same as those of the horizontal synchronous pulse. The equalization pulse remover(130) compares the horizontal synchronous pulse with the output pulse of the compared pulse generator(120), and removes the equalization pulse included in the horizontal synchronous pulse. The first through Nth deflectors(160A,160B-160N) performs horizontal deflection using horizontal synchronous pulses with different frequencies. The switch(150) supplies the horizontal synchronous pulse from the equalization pulse remover(130) to one of the first through Nth deflectors(160A,160B-160N). |
---|