METHOD FOR MANUFACTURING TRENCH ISOLATION LAYER OF SEMICONDUCTOR DEVICES

PURPOSE: A fabrication method of an extended trench isolation layer is provided to prevent an INWE(inverse narrow width effect) and an NWE(narrow width effect) by protecting an oxidation of a gate electrode using a spacer. CONSTITUTION: A method for manufacturing a trench isolation layer of semiconductor devices comprises the steps of sequentially forming a gate oxide(1), a poly crystalline silicon layer(2) and a silicon nitride(3) on a substrate, exposing the substrate corresponding to an isolation region by patterning, forming an oxide spacer(7) at side walls of the etched silicon nitride(3), poly crystalline silicon layer(2) and gate oxide(1), etching the exposed substrate using the spacer(7) and the silicon nitride(3) as a mask, forming a sacrificial oxide(4) to remove defects of the etched substrate, forming an isolating layer(5), and flattening the isolating layer(5) using the silicon nitride(3) as a stopping layer. 실리콘기판 식각공정 이전에 스페이서막을 형성하고 실리콘기판을 식각하여 희생산화막 형성시 제1다결정실리콘막의 산화를 방지하여 채널영역의 감소가 없고 노광능력보다 더 작은 소자분리영역을 형성하며, 후속 열공정에 의하여 불순물의 증가 또는 감소가 발생하는 영역이 채널영역에 포함되지 않음으로써 INWE나 NWE와 같은 비정상적인 소자특성이 없는 반도체소자의 연장형 트렌치 소자분리막을 제조한다.