APPARATUS AND METHOD OF DIGITAL CLOCK AND DATA RECOVERY

For an apparatus of a digital clock and data recovery (CDR), the present invention comprises: a frequency detector which determines whether a clock frequency is faster than a data rate of input data to detect high frequency (FH), low frequency (FL), and ultra-high frequency (FUH) signals, and based on the FH, FL, and FUH signals, generates continuous frequency up (CFUP) and continuous frequency down (CFDN) signals; and a digital loop filter (DLF) which controls by using the CFUP and CFDN signal to adjust the clock frequency in a coarse phase, and the FH and FL signals to adjust the clock frequency in a fine phase. According to the present invention, data loss can be minimized. 본 발명은 디지털 클럭 데이터 복원(CDR: Clock and Data Recovery) 장치에 있어서, 입력 데이터의 데이터 레이트(data rate)보다 클럭 주파수(clock frequency)가 빠른지 여부를 판단하여, FH(High Frequency), FL(Low Frequency), FUH(Utra-high Frequency) 신호를 검출하고, 상기 FH, FL 및 FUH 신호를 기반으로 CFUP(Continuous Frequency Up) 및 CFDN(Continuous Frequency Down) 신호를 생성하는 주파수 검출기와, 상기 CFUP 및 CFDN 신호를 이용하여 코스(coarse) 단계의 클럭 주파수를 조정하고, 상기 FH 및 FL 신호를 이용하여 파인(fine) 단계의 클럭 주파수를 조정하도록 제어하는 디지털 루프 필터(DLF: Digital Loop Filter)를 포함한다.