POWER LOSS PROTECTION INTEGRATED CIRCUIT USING LOW VOLATAGE CAPACITOR

The present invention relates to a power loss protection integrated circuit. By placing a blocking element on the electrical path between an output terminal of a converter and a low-field charging capacitor, during initial startup, the current flow to the low-field charging capacitor voltage is limi...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: CHAE JONGCHUL, LIM JINUP, KIM SEONHO, JANG KICHANG
Format: Patent
Sprache:eng ; kor
Schlagworte:
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Beschreibung
Zusammenfassung:The present invention relates to a power loss protection integrated circuit. By placing a blocking element on the electrical path between an output terminal of a converter and a low-field charging capacitor, during initial startup, the current flow to the low-field charging capacitor voltage is limited to ensure the stability of the output voltage of a buck converter. After a certain period of time, when the low-field charging capacitor voltage and the output voltage of the buck converter become almost the same, the blocking element is fully turned on and electrically connects the low-field charging capacitor voltage and the output voltage of the buck converter. 본 발명은 전력손실보호 집적회로에 관한 것으로, 벅 컨버터의 출력단자와 저전계 충전 커패시터 사이의 전기적 경로 상에 차단 소자를 배치함으로써, 초기 기동 시에는 저전계 충전 커패시터 전압으로의 전류 흐름을 제한하여 벅 컨버터의 출력 전압의 안정성을 보장하고, 일정 시간 경과 후 저전계 충전 커패시터 전압과 벅 컨버터의 출력전압이 거의 동일하게 되면 차단 소자가 완전 턴온(fully turn-on)되어 저전계 충전 커패시터 전압과 벅 컨버터의 출력전압을 전기적으로 연결한다.