HIGH VOLTAGE SEMICONDUCTOR DEVICE and MANUFACTURING METHOD THEREOF
The present invention relates to a high voltage semiconductor element and a manufacturing method thereof. In the present invention, a channel region is secured by improving a semiconductor manufacturing process sequence to enable dopant injection at a desired point in a body region, the size of the...
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| creator | CHUNG JIN SEONG LEE TAE HOON |
| description | The present invention relates to a high voltage semiconductor element and a manufacturing method thereof. In the present invention, a channel region is secured by improving a semiconductor manufacturing process sequence to enable dopant injection at a desired point in a body region, the size of the channel region is reduced by reducing a tilt angle of a dopant, and the number of masks in a process is reduced by using one mask pattern for the body region and an LDD region.
본 발명은 고전압 반도체 소자 및 그 제조 방법에 관한 것이다. 본 발명은, 반도체 제조 공정 순서를 개선하여 바디 영역의 원하는 지점에 도펀트 주입이 가능하게 하여 채널 영역을 확보하며, 또 도펀트의 틸트 각을 줄여 채널 영역의 크기를 감소시키고, 바디 영역과 LDD 영역을 하나의 마스크 패턴을 사용하여 공정에서의 마스크 개수를 줄이도록 하는 것이다. |
| format | Patent |
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본 발명은 고전압 반도체 소자 및 그 제조 방법에 관한 것이다. 본 발명은, 반도체 제조 공정 순서를 개선하여 바디 영역의 원하는 지점에 도펀트 주입이 가능하게 하여 채널 영역을 확보하며, 또 도펀트의 틸트 각을 줄여 채널 영역의 크기를 감소시키고, 바디 영역과 LDD 영역을 하나의 마스크 패턴을 사용하여 공정에서의 마스크 개수를 줄이도록 하는 것이다.</description><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210305&DB=EPODOC&CC=KR&NR=102224364B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25551,76304</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210305&DB=EPODOC&CC=KR&NR=102224364B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHUNG JIN SEONG</creatorcontrib><creatorcontrib>LEE TAE HOON</creatorcontrib><title>HIGH VOLTAGE SEMICONDUCTOR DEVICE and MANUFACTURING METHOD THEREOF</title><description>The present invention relates to a high voltage semiconductor element and a manufacturing method thereof. In the present invention, a channel region is secured by improving a semiconductor manufacturing process sequence to enable dopant injection at a desired point in a body region, the size of the channel region is reduced by reducing a tilt angle of a dopant, and the number of masks in a process is reduced by using one mask pattern for the body region and an LDD region.
본 발명은 고전압 반도체 소자 및 그 제조 방법에 관한 것이다. 본 발명은, 반도체 제조 공정 순서를 개선하여 바디 영역의 원하는 지점에 도펀트 주입이 가능하게 하여 채널 영역을 확보하며, 또 도펀트의 틸트 각을 줄여 채널 영역의 크기를 감소시키고, 바디 영역과 LDD 영역을 하나의 마스크 패턴을 사용하여 공정에서의 마스크 개수를 줄이도록 하는 것이다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHDy8HT3UAjz9wlxdHdVCHb19XT293MJdQ7xD1JwcQ3zdHZVSMxLUfB19At1c3QOCQ3y9HNX8HUN8fB3UQjxcA1y9XfjYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXx3kGGBkZGRibGZiZOTobGxKkCAOELLJM</recordid><startdate>20210305</startdate><enddate>20210305</enddate><creator>CHUNG JIN SEONG</creator><creator>LEE TAE HOON</creator><scope>EVB</scope></search><sort><creationdate>20210305</creationdate><title>HIGH VOLTAGE SEMICONDUCTOR DEVICE and MANUFACTURING METHOD THEREOF</title><author>CHUNG JIN SEONG ; LEE TAE HOON</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR102224364BB13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHUNG JIN SEONG</creatorcontrib><creatorcontrib>LEE TAE HOON</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHUNG JIN SEONG</au><au>LEE TAE HOON</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>HIGH VOLTAGE SEMICONDUCTOR DEVICE and MANUFACTURING METHOD THEREOF</title><date>2021-03-05</date><risdate>2021</risdate><abstract>The present invention relates to a high voltage semiconductor element and a manufacturing method thereof. In the present invention, a channel region is secured by improving a semiconductor manufacturing process sequence to enable dopant injection at a desired point in a body region, the size of the channel region is reduced by reducing a tilt angle of a dopant, and the number of masks in a process is reduced by using one mask pattern for the body region and an LDD region.
본 발명은 고전압 반도체 소자 및 그 제조 방법에 관한 것이다. 본 발명은, 반도체 제조 공정 순서를 개선하여 바디 영역의 원하는 지점에 도펀트 주입이 가능하게 하여 채널 영역을 확보하며, 또 도펀트의 틸트 각을 줄여 채널 영역의 크기를 감소시키고, 바디 영역과 LDD 영역을 하나의 마스크 패턴을 사용하여 공정에서의 마스크 개수를 줄이도록 하는 것이다.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | HIGH VOLTAGE SEMICONDUCTOR DEVICE and MANUFACTURING METHOD THEREOF |
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