SEMICONDUCTOR CHIP PACKAGE, CHIP SET AND METHOD FOR FABRICATING SEMICONDUCTOR CHIP
A semiconductor chip package, a chip set, and a method of manufacturing a semiconductor chip are provided to allow target level security by extending a voltage trimming range. A semiconductor chip package has a laminate structure of a DC chip(30) and at least one main chips(20a,20b). The DC chip inc...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | A semiconductor chip package, a chip set, and a method of manufacturing a semiconductor chip are provided to allow target level security by extending a voltage trimming range. A semiconductor chip package has a laminate structure of a DC chip(30) and at least one main chips(20a,20b). The DC chip includes a DC generation circuits generating DC voltages necessary for an operation of the main chips. The main chip includes circuits responding a DC signal generated by at least one circuit among the DC generation circuits. The DC generation circuits include at least one of a VCCH generation circuit for initialization, a reference voltage generation circuit generating a reference voltage, an array voltage and peripheral voltage generation circuit generating an array voltage and a peripheral voltage, a VPP generation circuit boosting a voltage of a word line, and a VBB generation circuit biasing a memory cell. |
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