METHOD OF MANUFACTURING ARRAY SUBSTRATE OF LCD DEVICE

A method for manufacturing an array substrate of an LCD is provided to prevent a via-hole for exposing a drain electrode from being over-etched when a contact hole for exposing a gate pad and the via-hole are simultaneously formed in a passivation layer. A pad part(A) and a TFT(Thin Film Transistor)...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: YOO, SEONG YEOL, JANG, BYEONG HYEON, CHOI, HYUNG SUK
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A method for manufacturing an array substrate of an LCD is provided to prevent a via-hole for exposing a drain electrode from being over-etched when a contact hole for exposing a gate pad and the via-hole are simultaneously formed in a passivation layer. A pad part(A) and a TFT(Thin Film Transistor) part(B) are defined on a glass substrate(110). A first metal layer is formed on the glass substrate. A first photoresist pattern having different thicknesses is formed on the first metal layer. The first metal layer is selectively etched by using the first photoresist pattern as an etching mask to respectively form a gate pad(120a) and a gate electrode(120b) in the pad part and the TFT part. The first photoresist pattern is removed in the TFT part, and partially removed in the pad part. A gate insulating layer(140) and an active layer(150) are sequentially formed on the resultant substrate to cover the gate pad, the gate electrode, and the remaining first photoresist pattern. A second photoresist pattern is formed on the active layer. The active layer is selectively etched by using the second photoresist pattern as an etching mask. The first and second photoresist patterns are removed. A second metal layer is formed on the resultant substrate. The second metal layer is selectively etched to respectively form source and drain electrodes(170b) and a sub second metal layer(170b) in the TFT part and the pad part. A passivation layer(180) is formed on the resultant substrate. The passivation layer is selectively etched to respectively form a contact hole(191) and a via-hole(192) in the pad part and the TFT part. An ITO(Indium Tin Oxide) layer is formed on the resultant substrate, and selectively etched to form an ITO electrode(210b) and a sub ITO layer(210a). The ITO electrode is contacted with the drain electrode through the via-hole, and the sub ITO layer is contacted with the gate pad through the contact hole.