HIGH-SPEED LATCH COMPARATOR

A high-speed latch comparator is provided to remove the phenomena missing the timing due to clock skew phenomena in high-speed and the delay time in the circuit by maintaining high output during half-period clock in which the latch comparator is not operated as a comparator. In a first latch circuit(110), a current path is connected to a power supply voltage and between a first node(Nd1) and a second node(Nd2), and a gate is cross-coupled with the other drain. In a second latch circuit(120), the current path is connected between the first node(Nd1) and a ground voltage and between the second node(Nd2) and the ground voltage, and a gate is cross-coupled with the other drain. In a first input circuit(130), the current path is connected between the first node(Nd1) and the ground voltage, is installed with the second latch circuit(120) in parallel and receives an input signal and a clock signal. In a second input circuit(140), the current path is connected between the second node(Nd2) and the ground voltage, is installed with the second latch circuit(120) in parallel and receives the input signal and the clock signal. In a third latch circuit(150), the current path is connected between the power supply voltage and the first output terminal and the second output terminal, a gate is cross-coupled with the other drain and is connected to the first latch circuit(110) in parallel. In a first common voltage maintaining unit(160), the current path is connected between the first output terminal and the ground voltage. The gate is connected to the gate of the first node(Nd1) and maintains the threshold voltage close to the common mode voltage. In a second common voltage maintaining unit(170), the current path is connected between the second output terminal and the ground voltage. The gate is connected to the gate of the second node(Nd2) and maintains the threshold voltage close to the common mode voltage.